Reliably producing submicron and smaller features is one of the challenges for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the miniaturization of circuit technology continues, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. For example, as circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease while the thickness of the dielectric layers remains substantially constant, with the result of increasing the aspect ratios of the features.
Sputtering, also known in one application as physical vapor deposition (PVD), is a method of forming metallic features in integrated circuits. In such applications, sputtering deposits a material layer on a substrate. A source material, such as a target, is bombarded by ions strongly accelerated by an electric field. The bombardment ejects material from the target, and the material then deposits on the substrate. In other applications however, sputtering may also be used to etch a substrate. The inventors have observed that, during deposition and etching, ejected particles may travel in varying directions, rather than generally orthogonal to the substrate surface, undesirably resulting in non-uniform deposition and etching of the substrate. In addition, other factors, such as process conditions or process chamber design, can also undesirably affect processing uniformity on the substrate.